The invention relates to analog-to-digital converters of the successive approximation type, and more specifically to an improved successive approximation register that operates at very high speeds with no race conditions.
There is a continuing, increasing need for high speed, low cost analog-to-digital converters to receive analog signals from various transducers and the like, for the purpose of rapidly converting the analog signals to digital numbers that can be input to a digital computer. The stat-of-the-art is generally indicated by the Am2502/3/4 successive approximation registers, manufactured by Advanced Micro Devices and others. These successive approximation registers are TTL high speed special purpose registers that contain all of the storage and digital control circuitry for an 8 or 12 bit analog-to-digital converter of the successive approximation type. Successive approximation analog-to-digital converters operate by comparing an unknown analog input with a time-dependent feedback voltage derived from a digital-to-analog converter. The conversion process is performed by generating N successive approximation numbers one bit at a time, beginning with the most significant bit.
FIG. 1 shows a basic block diagram of a successive approximation analog-to-digital converter. An analog input voltage V.sub.IN is applied to analog input terminal 1. The analog-to-digital converter 2 converts V.sub.IN into a digital representation of V.sub.IN by applying V.sub.IN across a resistor R. The other terminal of resistor R is connected by conductor 3 to the inverting input of comparator 5 and to the output of an N bit digital-to-analog converter 4. The non-inverting input of comparator 5 is connected to a ground reference voltage, so conductor 3 in effect functions as a "virtual ground" during the successive approximation procedure. A current I.sub.IN thus flows through resistor R. The digital-to-analog converter 4 produces an output current I.sub.DAC corresponding to the digital approximation number being applied to its N digital inputs on N conductors 8. The output of comparator 5 is connected by comparator data conductor 6 to an input of a successive approximation register (SAR) 7. For the first iteration of the method, the most significant bit produced by the successive approximation register 7 is output as a "0", with the remaining bits being "1's". The successive approximation register 7 then contains the first approximation number or "trial" binary number, which lies in the center of the range of possible digital equivalents to V.sub.IN. The first digital approximation number is apllied to the inputs of the digital-to-analog converter 4. A digital-to-analog conversion is made, and the resulting output current I.sub.DAC is effectively compared to I.sub.IN at node 3. If the input current I.sub.IN is larger than I.sub.DAC, then the voltage on conductor 3 will be at a positive potential and comparator will 5 produce a "0" on data comparator output conductor 6, which indicates that the first bit of the digital number into which V.sub.IN is to be converted is to be a "0". Otherwise, the first bit is to be a "1". Next, successive approximation register 7 produces a second digital approximation number in which the most significant bit is either a "0" or a "1", depending on the state of comparator output conductor 6, the second most significant bit is a "0", and the remaining bits are "1's". Then a third approximation number is produced in which the two most significant bits of the desired digital number are included. The procedure is repeated for the remaining N-2 bits, at which point the analog-to-digital conversion is complete, whereupon conductor 3 is at nearly zero volts.
The successive approximation register used in the above-mentioned Am2502 and related products can be utilized to implement successive approximation register 7 of FIG. 1. However, that successive approximation register has longer signal propagation delays than desirable in each bit. Furthermore, that successive approximation register is subject to internal signal "race" conditions, which necessitate building in larger then desirable safety margins to ensure proper operation under worst case conditions.
As the state-of-the-art has advanced, a clear need has arisen for a faster, less "delay-sensitive" successive approximation register than previously has been available in order to meet the goal of providing an inexpensive, high speed, high resolution (i.e., 12 bits) analog-to-digital converter.